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data sheet no. pd60294 IRS21853SPBF features ? gate drive supply range from 10 v to 20 v ? under voltage lockout for v cc & v bs1,2 ? 5 v input logic compatible ? tolerant to negative transient voltage ? matched propagation delays for all channels ? rohs compliant descriptions dual high side driver ic product summary v offset 600 v max v out 10 v to 20 v t on /t off (typ) 170 ns/170 ns i o+/- 2 a/2 a delay matching 40 ns package 16-lead soic (narrow body ) typical connection diagram +vdc1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vcc com hin1 hin2 vb1 ho1 vs1 vb2 ho2 vs2 irs21853 son16 +vdc2 the irs21853 is a high voltage, high speed powe r mosfet and igbt dual high-side driver with propagation delay matched output channels. proprietary hvic and latch immune cmos technologies enable ruggedized monolithic construction. t he floating logic input is compatible with standard cmos or lsttl output, down to 3.3 v logic and can be operated up to 600 v above the ground. the output dr iver features a high pulse current buffer stage designed for minimum driver cross- conduction. the floating channel can be used to drive an n-channel power mosfet or igbt in the high-side configuration, which operates up to 600 v.
IRS21853SPBF 2 typical connection diagram for er circuit in pdp cp c erc l er c 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vcc com hin1 hin2 vb1 ho1 vs1 vb2 ho2 vs2 irs21853 son16
IRS21853SPBF 3 absolute maximum ratings absolute maximum ratings indicate sustained limits bey ond which damage to the device may occur. all voltage parameters are absolute volt ages referenced to com. symbol definition min max units v cc low side supply voltage -0.3 20 (note1) v in logic input voltage (hin1,2) com-0.3 v cc +0.3 v b1,2 high side floating well supply voltage -0.3 620 (note1) v s1,2 high side floating well supply return voltage v b1,2 -20 v bn +0.3 v ho1,2 floating gate drive output voltage v s1,2 -0.3 v bn +0.3 v dv s /dt allowable v s1,2 offset supply transient re lative to com - 50 v/ns p d package power dissipation @ t a +25 oc - 1.25 w r ja thermal resistance, junction to ambient - 100 oc/w t j junction temperature t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) - 300 oc note1: all supplies are fully tested at 25 v. an internal 20 v clamp exists for each supply. recommended operating conditions for proper operation, the devic e should be used within the recommended conditi ons. all voltage param eters are absolute voltages referenced to com. the offset rating are tested with supplies of (v cc -com)=(v b1,2 -v s1,2 )=15 v. symbol definition min max units v cc low side supply voltage 10 20 v in hin1, 2 input voltage com vcc v b1,2 high side floating well supply voltage v s1,2 +10 v s1,2 +20 v s1,2 high side floating well supply offset voltage note 2 600 v ho1,2 floating gate drive output voltage v s1,2 v b1,2 v t a ambient temperature -40 125 oc note 2: v s1,2 and v b1,2 voltages will be tolerant to short negative transient spikes. these will be defined and specified in the future. note 3: logic operation for v s of ?5 v to 600 v. logic state held for v s of ?5 v to ?v bs1,2 . (please refer to design tip dt97-3 for more details).
IRS21853SPBF 4 static electrical characteristics (v cc -com)=(v b1,2 -v s1,2 )=15 v. t a = 25 o c unless otherwise specified. the v in , v in,th , and i in parameters are referenced to com. the v o and i o parameters are referenced to respective v s1,2 and are applicable to the respective output leads ho1,2. the v ccuv parameters are referenced to com. the v bsuv1,2 parameters are referenced to v s1,2 . symbol definition min typ max units test conditions v ccuv + v cc supply undervoltage positive going threshold 8.0 8.9 9.8 v ccuv - v cc supply undervoltage negative going threshold 7.4 8.2 9.0 v bsuv+ v bs1,2 supply undervoltage positive going threshold 8.0 8.9 9.8 v bsuv- v bs1,2 supply undervoltage negative going threshold 7.4 8.2 9.0 v i lk1,2 high-side floating well offset supply leakage current --- --- 50 v b1,2 = v s1,2 = 600 v i qbs quiescent v bs supply current --- 75 150 i qcc quiescent v cc supply current --- 110 220 a hin1,2 = 0 v or 5 v v ih logic ?1? input voltage 3.5 --- --- v il logic ?0? input voltage --- --- 0.6 v oh ho1,2 high level output voltage, v bias -v o --- --- 1.4 i o = 0 a v ol ho1,2 low level output voltage, v o --- --- 0.0 6 v i o =20 ma i in+ logic ?1? input bias current --- 5 20 v hin1,2 =5 v i in- logic ?0? input bias current --- --- 5 a v hin1,2 =0 v i o+ output high short circuit pulsed current ho1,2 --- 2 --- v o =0 v,v in =0 v, pw<=10 s i o- output low short circuit pulsed current ho1,2 --- 2 --- a v o =15 v,v in =5 v, pw<=10 s
IRS21853SPBF 5 dynamic electrical characteristi cs (all values are target data) (v cc -com)= (v b1,2 -v s1,2 )=15 v. t a = 25 o c unless otherwise specified. c l = 1000 pf unless otherwise specified. all parameters are reference to com. s y mbol definition min t yp max units test conditions t on turn-on propagation delay (ho1,2) --- 170 --- (v s1,2 -com)=0 v t off turn-off propagation delay (ho1,2) --- 170 --- (v s1,2 -com)=600 v t r turn-on rise time --- 15 50 t f turn-off fall time --- 15 50 mt delay matching (note 1) --- --- 40 ns note 4:max ( t on , ho1 , t on,ho2 )- min ( t on,ho1 , t on,ho2 ); max( t off,ho1 , t off,ho2 )- min ( t off,ho1 , t off,ho2 )
IRS21853SPBF 6 functional block diagram hin1 hin2 filter, latch uv detect driver vb2 vs2 ho2 level shift up level shift up filter, latch uv detect driver vb1 vs1 ho1 highside channle1 highside channel2 pulse gen pulse gen vcc com vccuv detect 5 v vreg
IRS21853SPBF 7 lead definitions symbol description vcc low side supply voltage com ground vb1,2 high side gate drive floating supply ho1,2 high side driver outputs vs1,2 high voltage floating supply return hin1,2 logic inputs for high si de gate driver outputs (in phase) lead assignments 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vcc com hin1 hin2 vb1 ho1 vs1 vb2 ho2 vs2 irs21853 sonic16
IRS21853SPBF 8 in out t r 50% 90% 10% 50% 90% 10% t off t f t on figure 1: switching time waveforms ho1,2 hin1,2 figure 2: input/output timing diagram
IRS21853SPBF 9 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-on delay time (ns) figure 3a. turn-on time vs. tem p erature ty p. 0 10 0 200 300 400 50 0 10 12 14 16 18 2 0 v bias supply voltage (v) turn-on delay time (ns) figure 3b. turn-on time vs. supply voltage typ. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-off time (ns) figure 4a. turn-off time vs. tem perature ty p. 0 100 200 300 400 500 10 12 14 16 18 20 v bias supply voltage (v) turn-off time (ns) figure 4b. turn-off time vs. supply voltage ty p. 0 20 40 60 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-on rise time (ns) figure 5a. turn-on rise time vs.tem p erature ty p. 0 20 40 60 10 12 14 16 18 20 v bias supply voltage (v) turn-on rise time (ns) figure 5b. turn-on rise time vs. supply voltage ty p.
IRS21853SPBF 10 0 20 40 60 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-off fall time (ns) figure 6a. turn-off fall time vs. tem p erature ty p. 0 20 40 60 10 12 14 16 18 2 0 v bias supply voltage (v) turn-off fall time (ns) figure 6b. turn-off fall time vs. supply voltage typ. 1 2 3 4 5 6 -50 -25 0 25 50 75 100 125 temperature ( o c) input voltage (v ) figure 7a. logic "1" input voltage vs. tem perature mi n. 1 2 3 4 5 6 10 12 14 16 18 20 v cc supply voltage (v) input voltage (v ) figure 7b. logic "1" input voltage vs. supply voltage min. 0 1 2 3 4 -50 -25 0 25 50 75 100 125 temperature ( o c) input voltage (v ) figure 8a. logic "0" input voltage vs. tem perature max. 0 1 2 3 4 10 12 14 16 18 20 v cc supply voltage (v) input voltage (v ) figure 8b. logic "0" input voltage vs. supply voltage max
IRS21853SPBF 11 0.0 0.5 1.0 1.5 2.0 -50 -25 0 25 50 75 100 125 temperature ( o c) high level output voltage (v ) figure 9a. high level output vs. tem perature max. 0.0 0.5 1.0 1.5 2.0 10 12 14 16 18 20 v cc supply voltage (v) high level output voltage (v ) figure 9b. high level output vs. supply voltage max. 0.00 0.05 0.10 0.15 0.20 -50 -25 0 25 50 75 100 125 temperature ( o c) low level output voltage (v) figure 10a. low level output vs.temperature max. 0.00 0.05 0.10 0.15 0.20 10 12 14 16 18 2 0 v cc supply voltage (v) low level output voltage (v) figure 10b. low level output vs. su pp l y volta g e max. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) offset supply leakage current (ua ) max. figure 11a. offset supply leakage current vs. tem perature 0 100 200 300 400 500 0 100 200 300 400 500 600 v b boost voltage (v) offset supply leakage current (ua ) max. figure 11b. offset supply leakage current vs. supply voltage
IRS21853SPBF 12 0 100 200 300 400 -50 -25 0 25 50 75 100 125 temperature ( o c) v bs supply current (ua) figure 12a. v bs supply cur re nt vs. temperature ty p. max. 0 100 200 300 400 10 12 14 16 18 20 v bs supply voltage (v) v bs supply current (ua) figure 12b. v bs supply cur re nt vs. supply voltage ty p. max. 0 200 400 600 -50 -25 0 25 50 75 100 125 temperature ( o c) v cc supply current (ua) figure 13a. v cc supply curre nt vs. tem perature max. t yp . 0 200 400 600 10 12 14 16 18 2 0 v cc supply voltage (v) v cc supply current (ua) figure 13b. v cc supply cur re nt vs. supply voltage max. ty p. 0 10 20 30 40 50 60 -50 -25 0 25 50 75 100 125 logic "1" input current (ua ) figure 14a. logic "1" input current vs. tem perature max. ty p. temperature ( o c) 0 10 20 30 40 50 60 10 12 14 16 18 20 v cc supply voltage (v) logic "1" input current (ua ) figure 14b. logic "1" input current vs. supply voltage max. ty p.
IRS21853SPBF 13 0 2 4 6 8 10 -50 -25 0 25 50 75 100 125 temperature ( o c) logic "0" input current (ua ) figure 15a. logic "0" input current vs. tem perature max. 0 2 4 6 8 10 10 12 14 16 18 2 0 v cc supply voltage (v) logic "0" input current (ua ) figure 15b. logic "0" input current vs. supply voltage max. 6 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 temperature ( o c) v cc uvlo threshold (+) (v) figure 16. v cc undervoltage threshold (+) vs. tem perature max. ty p. min. 6 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 temperature ( o c) v cc uvlo threshold (-) (v) figure 17. v cc undervoltage threshold (-) vs. tem perature max ty p. min. 6 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 temperature ( o c) v bs uvlo threshold (+) (v) figure 18. v bs undervoltage threshold (+) vs. tem perature max. ty p. min. 6 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 temperature ( o c) v bs uvlo threshold (-) (v) figure 19. v bs undervoltage threshold (-) vs. tem perature max ty p. min.
IRS21853SPBF 14 0 2 4 6 8 -50 -25 0 25 50 75 100 125 temperature ( o c) output source current (a ) figure 20a. output source current vs. tem perature ty p. 0 2 4 6 8 10 12 14 16 18 2 0 v bias supply voltage (v) output source current (a ) figure 20b. output source current vs. supply voltage ty p. 0 2 4 6 8 -50 -25 0 25 50 75 100 125 temperature ( o c) output sink current (a ) figure 21a. output sink current vs.temperature ty p. 0 2 4 6 8 10 12 14 16 18 20 v bias supply voltage (v) output sink current (a ) figure 21b. output sink current vs. supply voltage ty p. -12 -10 -8 -6 -4 -2 0 10 12 14 16 18 20 v bs floting supply voltage (v) v s offset supply voltage (v ) figure 22. maxim um v s negative offset vs. supply voltage ty p.
IRS21853SPBF 15 notes: 1. dimensioning & tolerancing per ansi y14.5w-1982 2. controlling dimension. millimeter 3. dimensions are shown in millimeter [inches] 4. outline conforms to jedec outline ms-012ac 5. dimension is the length of lead for soldering to a substrate 6. dimension does not include mold protusions. mold protusions shall not exceed 0.15 [.006] 16-lead soic (narrow body)
IRS21853SPBF 16 carrier tape dimension for 16soicn code min max min max a 7.90 8.10 0.311 0.318 b 3.90 4.10 0.153 0.161 c 15.70 16.30 0.618 0.641 d 7.40 7.60 0.291 0.299 e 6.40 6.60 0.252 0.260 f 10.20 10.40 0.402 0.409 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 16soicn code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 22.40 n/a 0.881 g 18.50 21.10 0.728 0.830 h 16.40 18.40 0.645 0.724 metric imperial e f a c d g a b h n ote : controlling dimension in mm loaded tape feed direction a h f e g d b c
IRS21853SPBF 17 so-16n package is msl3 qualified. this product has been designed and qualified for the industrial level. qualification standards can be found at ir?s web site http://www.irf.com/ world headquarters: 233 kansas st., el segundo, ca lifornia 90245 tel: (310) 252-7105 data and specifications subject to ch ange without notice 06/28/2007 order information 16-lead soic IRS21853SPBF 16-lead soic tape & reel irs21853strpbf

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